Field of the Invention
The inventive concepts relate to built-in self-test (BIST) units, for cache memories, which allow the integrated circuits (ICs) incorporating the cache memories to perform tests of the cache memories, for example for verification testing during IC manufacture.
As the technology for making integrated circuitry, such as memory devices, has advanced, more and more circuits and functions are built into one chip. There is a need to test all of the different functions of the circuits within each chip, for example, all of the memories and all of the read and write circuits, before the integrated circuit is usable in a particular product.
Hence, integrated memory circuits typically undergo device verification testing during manufacture. A specialized integrated circuit device tester may be used to perform such tests. The use of such equipment, however, increases the costs of manufacturing the memory circuits. In addition, for integrated circuit devices that provide large memory arrays, the cycle time required to perform such read/write tests increases in proportion to the size of the array.
To overcome difficulties and reduce costs associated with external testing of integrated circuit memories, integrated circuits have been constructed with built-in self-test (BIST) circuitry. Built-in self-have test units have many advantages over using external automatic test equipment (ATE). These include the ability to run at full speed using an on-board phase-locked loop (PLL) independently of the ATE timing and accuracy limitations, as well as a large reduction in the number of test vectors to be stored off-line. Memories are ideal candidates for BIST, since they are very regular structures, making the algorithms required to test them relatively easy to realize in hardware.
Cache memories, however, are harder to test since there is an associated tag memory, such as a content address memory (CAM), corresponding to each location in RAM, for storing the necessary tag for each entry which defines where new data is written and old data is read from. The conventional approach to built-in self-testing of a cache would be to logically divide the cache into two parts, the RAM array and the CAM array, and then perform separate tests on each part. The RAM would be tested using a normal RAM BIST engine; whereas the CAM probably would be tested by ad-hoc functional tests. Theoretically, the CAM array could be scan tested in such a separate test, if all CAM elements were scannable. Pattern generation would be completely automated, and releatively few scan patterns would be required. However, in some cache memory devices the CAM cells are not scannable.
One approach considered for self-testing of such non-scannable CAM cells might involve a separate ‘macrotest’ of the CAM cells, using the scan chains surrounding the cache to setup and observe results. For such a macrotest, assume that scan data can be shifted in, so that the CAM cells can be programmed in a single cycle following the scan chain shift. Only one CAM word can be written at a time. The CAM cells retain their state while the scan chains are shifting. Also, it would be assumed that observability of a hit on match lines is provided in a scannable flip-flop (FF). To observe the results of the CAM scan test then would require observation of the wordlines driven by the match logic output in scan FFs. In the best case, where it is possible to observe all match logic outputs separately, a basic stuck-at type test on the CAM array requires 2(N+(1+M)) cycles, where N is the number of CAM words and M is the CAM word width.
However, to perform such a test, it would be necessary to program the whole cache to known values O(N), match all lines simultaneously O(1), and then mismatch all lines simultaneously by a single bit O(M). The process must be repeated for true and complement data. For a CAM with a 4 bit field (including valid bit) and 1280 entries, the number of parallel patterns required is 2570. Assuming that this is a scan based test and that the scan chains are 400 FFs long, the total number of cycles needed is 400*2570=1,028,000 cycles. This is not acceptable for a macrotest length mainly because it consumes too much pin memory. More limited access to the match lines would drive the pattern count higher still, making a macrotest approach impractical.
As shown by the discussion above, there is a continuing need for a technique to efficiently implement built-in self-testing of a cache memory. To provide the necessary efficiency, there is an attendant need for testing the entire cache in a single operation, instead of requiring separate tests for the RAM and the CAM. There is a further need for a self-testing technique that requires a minimum amount of time. To be cost effective, any self-test device implemented on an IC must comprise a minimum amount of circuitry and/or require minimal real-estate on the chip.